The present invention relates to a semiconductor storage circuit (memory circuit), and more particularly, it relates to technology of a semiconductor storage circuit suitably included in a system LSI or an ASIC and a layout method for the semiconductor storage circuit.
The so-called memory embedded LSIs, such as a system on chip or a system LSI including both a logic circuit and a memory circuit on one chip and an ASIC (Application Specific Integrated Circuit) fabricated for specific use, have been recently remarkably developed so as to attain a larger circuit scale, more complicated functions and a higher operation speed. In accordance with the increase of the operation speed and the like, the storage capacity and the number of input/output terminals of a storage circuit included in a memory embedded LSI have been increasing.
The storage capacity and the I/O width required of a memory embedded LSI are varied depending upon user specification. Accordingly, in a conventional memory circuit, a driver circuit is provided in accordance with the maximum storage capacity and the maximum I/O width that a chip can possibly attain, and the driving ability of the driver circuit is set to the maximum value. Thus, the memory embedded LSI can cope with any user specification within the limits of functions that can be provided by the memory embedded LSI.
In order to ease the placement and routing and the layout design accompanied by the change of the number of memory cell arrays, technique to place circuits so as to relax crowdedness of wirings has been disclosed (in, for example, Japanese Laid-Open Patent Publication No. 2002-25251). In a memory according to this technique, however, a control signal line for controlling the operation of a memory cell array is driven intensively at an end of the memory cell array. In such an architecture, the ability of a driver circuit for driving the control signal line should be individually determined in accordance with storage capacity to be set, or should be large enough in accordance with the maximum possible storage capacity.
The architecture of a memory circuit used in a conventional memory embedded LSI is optimum when the storage circuit is realized with the maximum storage capacity and the maximum I/O width. In the case where an actually constructed storage circuit has comparatively small storage capacity and I/O width, however, a driver circuit designed in accordance with the maximum storage capacity and the maximum I/O width has excessive driving ability over the load of the storage circuit, and also wastefully occupies a limited circuit area within the chip. Furthermore, in a storage circuit such as a DRAM (Dynamic Random Access Memory) necessary to provide an internal power circuit, the electric power is wastefully consumed by the excessive driving ability of a driver circuit for the power supply.
On the other hand, in the case where the driving ability of a driver circuit is individually determined in accordance with the storage capacity and the I/O width to be set, the design is complicated, and there arises another problem that the development of another circuit with different storage capacity requires a long period of time and high cost.